XLS: Accelerated HW Synthesis
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XLS: Accelerated HW Synthesis
GitHub
Overview
Tutorials
Tutorials
Overview
DSLX
DSLX
Hello, XLS!
Basic logic
Intro to parameterics
For expressions
Enumerate and match
Intro to Procs
XLS[cc]
XLS[cc]
Overview
Integers
Channels
Memory
State
Pipelined Loops
FAQ
IR
IR
Overview
Semantics
Optimizations
Scheduling
Scheduling
Overview
Delay Estimation
Visualizer
Native JIT
Native JIT
Overview
Data Layout
Formal
DSLX
DSLX
Reference
Standard Library
Floating Point
Fuzzer
Interpreter
Language Server
Code Generation
Code Generation
Codegen Options
IR Lowering
VAST
Tools
Tools
Build System
Bazel Rules And Macros
Quick Start
Listing
Interpreters
Development
Development
Contributing
Style Guide
Adding a new IR operation
Ideas and Projects
FPGA characterization (experimental)
Design Docs
Design Docs
Legalize Multiple Channel Ops Per Channel
Proc-scoped channels
NoC
NoC
Overview
Topologies
Topologies
Overview
Dimension Order
Tree
k-ary n-fly Butterfly
Fully Connected
Star
Glossary
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