Navigating CFU Playground

CFU Playground is a collection of many different packages. Below we have outlined where some of the commonly asked for files are outside of developing a CFU. All paths specified begin from your local CFU-Playground root.

Software

  • General software (menus, microbenchmarks): common/src/
    • TFLM Models:common/src/models
  • LiteX low-level library source: third_party/python/litex/litex/soc/software/
  • TFLM (updated from upstream automatically): third_party/tflite-micro/
  • Project-specific source: proj/[project_name]/src

Precedence: The software build directory is constructed in multiple steps. First the original TFLM code is copied. Then any files under common/src will overlay TFLM files at the same paths; then finally any files in proj/[projct_name]/src will overlay any of the preceding and therefore take precedence.

Gateware

  • Your project CFU: proj/[project_name]/cfu.v if writing Verilog, proj/[project_name]/cfu.sv if writing SystemVerilog, or proj/[project_name]/cfu_gen.py if writing Amaranth. These top files can refer to other source files.
  • Amaranth infrastructure provided by CFU Playground: python/amaranth_cfu/
  • VexRiscv CPU RTL:soc/vexriscv/
  • Litex SoC source: third_party/python/lite*/

Hardware

  • Workflow for each board:soc/board_specific_workflows

Tools

  • RISC-V Compiler if using Conda: CFU-Playground/env/conda/envs/cfu-common/bin
  • OSS FPGA tools if using Conda: CFU-Playground/env/conda/envs/cfu-common/{bin,share,lib}
  • Renode: third_party/renode

Misc

  • Third Party: third_party/ (contains src for Renode, TFLM, and other python packages, etc. needed and used in CFU-Playground)

Generated by your builds

  • Software build: proj/[project_name]/build/src
  • Software binary: proj/[project_name]/build/software.bin
  • Softare disassembly: proj/[your project]/build/software.elf.dis
  • Gateware build: soc/build/[board].[project_name]/gateware/
    • LiteX-generated Verilog (not including CPU or CFU): soc/build/[board].[project_name]/gateware/[board].v
    • Synthesis Stats: soc/build/[board].[project_name]/gateware/[board].rpt (if using nextpnr)
    • Bitstream: soc/build/[board].[project_name]/gateware/[board].bit
  • Software info generated by LiteX: soc/build/[board].[project_name]/software/include/generated/*
    • the headers in this directory contain much useful information about your platform that software can use